What Makes a NIC a SmartNIC, and Why is it Needed?

There has been a lot of buzz recently in the industry regarding the use of SmartNICs (also known as intelligent server adapters (ISAs)) in cloud data center servers to boost performance by offloading CPUs in servers by performing network datapath processing. Of course, performing network offloads on the NIC is not new, with many traditional NICs supporting offload of functions like checksum and segmentation. However, with the recent tectonic shift in cloud data center networking driven by software-defined networking (SDN) and network functions virtualization (NFV), a new class of offload NIC is needed - namely the SmartNIC.

Why is a SmartNIC needed?
Specifically, there are three major reasons why a smart offload NIC, or SmartNIC, is needed:

1) The complexity of the server-based networking data plane has increased dramatically with the introduction of overlay tunneling protocols such as VXLAN, and virtual switching with complex actions.

2) Increasing network interface bandwidths mean that performing these functions in software creates an untenable load on the CPU resources, leaving little or no CPU left over to run applications.

3) A key requirement of SDN is that the networking data plane must remain fungible, so fixed-function offload technologies cannot be applied.

What exactly is a SmartNIC anyway?
The term SmartNIC is being bandied about quite a bit in the industry right now, and as is often the case with any new terminology, there is some confusion over the precise definition. Netronome’s perspective is that a SmartNIC must:

1) Be able to implement complex server-based networking data plane functions, including multiple match-action processing, tunnel termination and origination, metering and shaping and per-flow statistics, for example.

2) Support a fungible data plane either through updated firmware loads or customer programming, with little or no predetermined limitations on functions that can be performed.

3) Work seamlessly with existing open source ecosystems to maximize software feature velocity and leverage.

Server Offload Models
Let’s compare four basic models of server offload:

Model 1: Partial data plane offload using a fixed function NIC
In this case, a portion of the server networking data plane is implemented in and offloaded by the NIC. Typically, such a NIC is not programmable and hence the data plane implemented is fixed. For the features supported by the data plane implemented in the NIC silicon the packet forwarding is performed by the NIC, once a flow has been identified. The identified flow rules are stored in memory on-chip in the NIC. All traffic that relates to features not implemented by the NIC, or flows that are not stored in the memory on-chip in the NIC, are handled by the networking data plane in the host. Initial packets in a flow are handled by the networking data plane in the host. The performance of such an implementation is dependent on the percentage of data plane features implemented by the NIC and the number of flow rules that can be stored on-chip in the NIC.

Model 2: Partial data plane using a SmartNIC
In this case, a portion of the server networking data plane is implemented in and offloaded by the SmartNIC. Since the SmartNIC is programmable, new features available in the server networking data plane in the host can be implemented based on customer requests to match the features in the server networking data plane in the host. Typically, a SmartNIC includes larger memory on-chip or on the SmartNIC board to hold a much larger number of flows.

For the features supported by the data plane implemented in the SmartNIC, the packet forwarding is performed by the SmartNIC, once a flow has been identified. The identified flow rules are stored in memory on-chip or on the SmartNIC. All traffic that relates to features not implemented by the SmartNIC or flows that are not stored in the memory on-chip or on the SmartNIC are handled by the server networking data plane in the host. Initial packets in a flow are handled by the server networking data plane in the host. The performance of such an implementation is dependent on the percentage of data plane features implemented by the SmartNIC and the number of flow rules that can be stored on-chip or on the SmartNIC.

Model 3: Whole data plane offload using a SmartNIC
In this case, the server networking data plane is implemented in and offloaded by the SmartNIC. Since the SmartNIC is programmable, new features available in new versions of the server networking data plane in the host can be implemented in the SmartNIC to match the features in the server networking data plane in the host, thereby maintaining feature parity. Typically, a SmartNIC includes larger memory on-chip or on the SmartNIC board to hold a large number of flows.

For all packets, packet forwarding is performed by the SmartNIC once a flow has been identified. The identified flow rules are stored in memory on-chip or on the SmartNIC. Initial packets in a flow are handled by the server networking data plane in the host. All traffic that relates to flows not stored in the memory on-chip or on the SmartNIC ar

e handled by the server networking data plane in the host. The performance of such an implementation is dependent on the number of flow rules that can be stored on-chip or on the SmartNIC.

Model 4: Complete control plane and data plane offload using a SmartNIC
In this case, the server networking control plane and data plane are implemented in and offloaded by the SmartNIC. Since the SmartNIC is programmable, new features available in new versions of the control plane and data plane in the host can be implemented in the SmartNIC to match the features in the host, thereby maintaining feature parity. This model assumes there is no control or data plane in the host. Typically, a SmartNIC includes larger memory on-chip or on the SmartNIC board to hold a large number of flows. For all packets, packet forwarding is performed by the SmartNIC once a flow has been identified. The identified flow rules are stored in memory on-chip or on the SmartNIC. Initial packets in a flow are handled by the SmartNIC or in collaboration with a centralized SDN Controller that the SmartNIC is connected to. The performance of such an implementation is dependent on the number of flow rules that can be stored on-chip or on the SmartNIC.

Models supported by Netronome
Netronome Agilio CX ISAs (2x10GbE, 2x25GbE, 2x40GbE) are designed to support Models 2 and 3 with the Agilio Software available today. The Netronome Agilio CX ISAs include large on-chip memory and on the SmartNIC. With up to 2GB of DDR memory on the SmartNIC, up to 2M flow rules can be supported, helping boost performance significantly. Netronome Agilio CX ISAs include an Arm processor and in-band or out-of-band control mechanisms, making the hardware capable of supporting Model 4. Software support for Model 4 will be coming in a future release of the Agilio Software.